1. Field of the Invention
This invention relates to amplifiers in general and, more particularly, to unity gain buffer amplifiers.
2. Description of the Prior Art
Buffer amplifiers are widely used to provide isolation and/or low output impedance with minimal voltage offset from input to output. Typically, the input impedance of the amplifier is much higher than its output impedance. In applications where DC-containing signals are buffered, such as with voltage references, it is desirable that the voltage offset be minimized.
Prior art buffers, such as those shown in FIG. 1 of U.S. Pat. No. 4,639,685, have significant voltage offset because of the different emitter-base voltages (V.sub.BE) for PNP and NPN transistors. In the above-identified patent, the above problem is recognized and cancellation of the offset is attempted by having two of each polarity transistor in each signal path (there are two signal paths, one for pull-up, one for pull-down). However, the offset is only partially canceled because the current densities in the transistors are different.
Thus, it is desirable to provide a buffer design that can provide low voltage offset without a lot of complexity. It is also desirable to provide a technique which allows for multiple transistor conductivity type transistors in the signal path(s) while providing low voltage offset.